VoidSense / Rev 04.21
VSN-001 · Physical Reasoning Core CMMC 2.0 · L2 Track v0.9.4 · Alpha

The reasoning layer for the
sovereign industrial
stack.

VoidSense is the AI-native reasoning system for the physical economy — a self-improving, air-gapped platform that turns every factory line into a closed loop between the atoms on the floor and the bits in the design. Purpose-built where general-purpose AI cannot go.

Context Window
1.00M tok
False-Call Target
≤ 0.5%
Defect Escape
≤ 0.3%
Exploded orthographic render of a printed-circuit-board assembly bisected by a cyber-amber reference axis, showing the correspondence between physical layers and their digital twin
FIG.01 · PHYSICAL TWIN / DESIGN TWIN · CORRELATION AXIS GROUNDED
§ 02 / 07 THESIS

The logic of physical AI.

Autonomous manufacturing is a trillion-dollar market gated by a single bottleneck: the data doesn't exist. General-purpose AI will never cross the gap. VoidSense builds the substrate that does — and owns the distribution it's trained on.

The Problem

The physical economy is starved of training data.

Manufacturing data is scarce, noisy, and historical — locked inside obsolete components, legacy assemblies, and fab-notes the line was never built to expose. Every incumbent inspection vendor ships the same blind spot.

Frontier models, trained on the open web, cannot learn what the factory floor refuses to publish. The gap isn't capability. It's ground truth — and it will not close on its own.

Observed
28%
Inferred
47%
Missing
83%
The Solution

We manufacture the ground truth ourselves.

VoidSense runs a Physical Twin Simulation that generates physics-grounded data at a scale the real world can't — a proprietary corpus that compounds with every customer and cannot be replicated by a general-purpose lab.

A defect is reported only when physics says it's possible. Zero hallucination. Zero hand-wave. A durable moat, by construction.

Simulated
10⁶⁺
Verified
92%
Hallucinated
0.0%
§ 03 / 07 ARCHITECTURE

A stack competitors can't assemble.

Four components, each defensible on its own; together they compound into a reasoning loop between design intent, physical dynamics, and field deployment. Every layer earns its place against a measured baseline.

A · 01 / SYNTHETIC FOUNDRY

The data moat competitors cannot buy.

Our synthetic foundry produces the defect corpus the physical economy refuses to expose — distribution-matched, physics-grounded, and fully owned. It is the substrate under every capability we ship, and it compounds with every customer line we deploy.

RoleCORPUS · PRIOR
MatchDISTRIBUTION
DomainPCBA · SMT · AXI
Neural layer architecture condensing into an optical lens assembly that projects a synthetic chip die, rendered as an isometric grayscale schematic
FIG.02 · SYNTHETIC FOUNDRY ORTHOGRAPHIC
A · 02 / GROUNDED REASONING CORE

A reasoning core specialized on our own corpus.

An open-weight base, retrained on the Foundry's data, holds entire multi-modal project trees — CAD, netlists, fab-notes — in active memory. Every capability we ship is earned against a measured baseline, never presumed.

BaseOPEN-WEIGHT
EvidenceMEASURED BASELINE
ModalityCAD · NETLIST · PDF
A · 03 / INFERENCE GROUNDING

Zero-hallucination by architecture, not by prompt.

A neuro-symbolic grounding layer verifies every response against the deterministic topology of the customer's own project. A defect is reported only when the design logic says it's possible — the feature enterprise buyers refuse to ship without.

ReasoningNEURO-SYMBOLIC
ValidationOPEN BENCHMARK
InterfaceTOOL_CALL
A · 04 / SELF-IMPROVEMENT LOOP

A system that gets sharper every day it runs.

A defect-injection self-improvement loop hardens the model against adversarial cases generated in the Foundry. Each release must clear an empirical gate before it ships — and our unit economics improve with every line we deploy, widening the gap against any general-purpose competitor.

ModeSELF-IMPROVING
Ship RuleEMPIRICAL GATE
Failure ModeMIGRATE · NOT SHIP
Isometric rendering of a conveyor-line inspection cell with a robotic arm, an amber projection cone forecasting a future station's defect onto the current assembly
FIG.03 · INJECTION LOOP ISOMETRIC · 30°
§ 04 / 07 MARKET · NPI

The wedge: a reconciliation problem every PCBA line has.

New Product Introduction burns 5–7 manual design-to-fab cycles because no tool reconciles unstructured fab-notes with structured CAD. We collapse the loop to 2–3 — and earn a beachhead in every PCBA line in the world.

Case Study · NPI-01

From 5–7 cycles to 2–3.

By aligning unstructured PDF fab-notes with structured Gerber and AXI data, VoidSense collapses NPI cycles from 5–7 rounds to 2–3 — and, on the open PCBA-Reasoning-Bench (arXiv:2601.19222), doubles the accuracy of every general-purpose model tested. Real customer ROI, verifiable benchmark, measurable in weeks.

Iteration Reduction
−58%
Localization Accuracy
2.00× vs GP
Iter · Diagram / Traditional vs. VoidSense 2.3 cycles
RECONCILED
DESIGN FAB VoidSense
Mode
Reconciled
Cycles
2–3
Escape Rate
≤ 0.3%
§ 05 / 07 MODALITY

Defects no single sensor can see.

VoidSense catches failures that are invisible to any one modality by reasoning across them. Optical, X-ray, and thermal data fuse against a shared topology — a category of defect the installed base of single-modality vendors structurally cannot address.

Fusion is not a feature. It is the product.

We correlate Automated Optical Inspection, X-Ray, and thermal imagery against the same grounded topology. Disagreement between sensors is itself a signal — often the earliest and most valuable one the line will produce all week.

False-Call Rate
≤ 0.5%
Target
Defect Escape Rate
≤ 0.3%
Target
Modality Coverage
AOI · AXI · IR
Live
Correlation Δ
0.047
Nominal
Source · Internal VSN-MOD-CORR Benchmark, Q1 2026 arXiv:2601.19222 ↗
Method · PCBA-Reasoning-Bench · n=4,812 panels · 14 lines IPC-A-610H · ANSI/IPC-7095D
Inspection Stack · Modality Correlation
Isometric render of a PCB assembly showing Optical AOI, X-Ray AXI, and Thermal IR modalities converging on a shared amber prism over a U7 BGA site, with target metrics, modality coverage, a correlation metric, and a fusion confidence readout
§ 06 / 07 SOVEREIGN EDGE

The only defense-grade option on the board.

The Defense Industrial Base cannot send its process data to the cloud. VoidSense runs where the work happens — on local hardware, behind the air gap, against the standards the DIB already speaks. A market most vendors are structurally disqualified from.

Sovereign Edge

Local by default. Private by design. Defense-grade by standard.

Frontier reasoning, compressed to run inside a factory cell or a sealed enclosure — no round-trip, no exposure of process IP, no outside dependency. The posture that unlocks defense, aerospace, and regulated industrial budgets most cloud-first vendors will never touch.

PRINCIPLE Local compute · reasoning happens on the line, not in the cloud Core
PRINCIPLE IP containment · your process knowledge never leaves the site Core
PRINCIPLE Air-gap native · designed for networks that are not connected Core
STANDARD CMMC 2.0 Level 2 · the Defense Industrial Base baseline On Path
AIR-GAPPED · BY DESIGN Orthographic illustration of an enterprise reflow oven and a ruggedized edge compute appliance linked by an amber data loop, with a distilled synthetic model cube and a shield motif at the junction
Deployment
On-Prem · Edge
Network Model
Air-Gapped
Baseline Standard
CMMC 2.0 · L2
Tier · Premium defense configuration For mission-critical industrial environments
§ 07 / 07 TEAM

Rare founders for a rare problem.

Two founders with 30+ combined years across agentic systems, spatial AI, and high-performance hardware — the exact intersection this category requires, and almost nobody else has.

CEO · Systems Architect
Lead, Reasoning & Distributed Arch.

Former Systems Lead at a frontier Reality Labs group, driving agentic self-improving systems, and previously inside a major chipmaker's AI division. Was CTO of a CG deep-tech startup acquired by a leading social-media company. A veteran of high-stakes computer vision at a Hollywood-scale visual-effects studio. 3 patents filed in distributed architecture and real-time computer vision.

Experience
15 yrs · Systems Eng.
Patents
3 filed
CTO · Hardware & Software Lead
Lead, Silicon & Edge Inference.

Former Team Lead at a $300M agricultural-AI firm — the closest analog to our physical-AI thesis currently in-market. Technion-trained Electrical Engineer with 15 years shipping high-performance hardware at a flagship consumer-electronics company and multithreaded processor validation at a blue-chip semiconductor research lab.

Focus
EE · HPC · Edge
Training
Technion · 15 yr field

We're scoping a tight
investor round.