VoidSense is verification-quality tooling for chip design teams (RTL / SystemVerilog). We prove whether your tests would actually catch a real bug — before tape-out.
Your coverage says 100%.
Your tests catch what, exactly?
We prove it.
VoidSense is the independent escape-rate auditor for RTL verification. We inject realistic, behaviour-changing bugs into your design and prove whether your existing tests would catch them — module by module, with reproducing vectors, in your regression, every night. We grade the verification, not the design.
Coverage measures what ran. Not what you'd catch.
Every team ships on green coverage. But a testbench can execute 100% of your lines and check almost none of them — and that gap is exactly where escaped bugs and silicon re-spins come from. First-silicon success just hit a 20-year low.
Green coverage is a false sense of security.
Code coverage proves a line executed. It says nothing about whether any checker would fire when a realistic bug appears. Teams sign off on 100% coverage over testbenches that assert next to nothing — and the first time anyone finds out is a respin.
First-silicon success fell to 14% in 2024, the lowest in the 20-year Wilson study. Logic and functional bugs remain the #1 respin cause — each one a full re-spin and months of lost schedule.
We measure escapes, not execution.
VoidSense asks the only question that predicts silicon: if a realistic bug were introduced here, would your tests catch it — yes or no? We plant provable, behaviour-changing bugs and report the ones that escape, each with the exact input vector that reproduces it.
It's falsifiable, CI-friendly, and vendor-neutral — it grades any team's tests, and any AI agent's, including the ones now writing your RTL.
Mutation testing, made faithful enough to trust.
This is mutation testing / testbench qualification — an idea the industry has had for years and shelved, because the legacy tools buried teams in unrealistic, unkillable, equivalent mutants. VoidSense is built to be faithful: it reads a design the way an engineer does — RTL and spec together — so the bugs it plants are the ones your silicon would actually see, and every gap it reports is a real one. And it is independent — it grades any team's verification, or any AI agent's, because it never writes the tests it judges.
The bugs your silicon would actually see.
Legacy tools flip an operator and call it a fault. VoidSense plants the failures engineers really ship — the subtle logic, datapath, and control errors that slip past review and reach silicon — grounded in how real designs break. That realism is what makes a missed one worth acting on.
Every escape is real — not noise.
The false positives that shelved legacy mutation tools are engineered out. VoidSense reasons about a design across layers — the logic itself, the spec behind it, and the gaps between spec and RTL — so a reported escape is a genuine hole in your verification, never an unkillable or equivalent artifact you waste a day dismissing. Trust is the whole product.
Graded against the flow you already trust.
An escape only matters if it would survive the verification you actually sign off on. VoidSense measures against your real environment — your regressions, your coverage, your formal — so a finding means your signoff would miss it, not merely a unit test. It meets your flow where it is; it doesn't ask you to adopt a new one.
Who watches the watchmen?
When the same class of model writes your RTL and your tests, they share blind spots. VoidSense is the independent layer that grades any team's — or any AI agent's — verification, and runs as a gate in your CI. Neutrality is a promise no copilot can honestly make about its own output.
The wedge: a test-quality gap every RTL team has.
Point the auditor at a block and it makes the blind spots every RTL codebase hides impossible to ignore — tests that run green but check almost nothing, logic no test in the suite would ever exercise, and RTL that quietly contradicts its own spec. On a design of any size, from a single IP to a full SoC.
The gaps hiding behind green coverage.
Every audit returns the same uncomfortable classes of finding: tests that execute but assert nothing, so a real bug passes silently; behaviour no test in the suite would ever catch; and places where the RTL and its own spec disagree. Each is ranked by severity and comes with a concrete scenario that reproduces it — a worklist, not a wall of noise.
The bugs your coverage can't see.
One defensible number the tapeout review can act on: your escape rate, per module, with an honest confidence label on every finding — a signoff-grade audit trail for a tapeout or functional-safety (ISO 26262) review, never a black-box score.
A metric, not a vibe.
We report a defensible escape rate per module, and stand behind every finding with a reproducing scenario and an honest confidence label. No inflated kill rates, no hidden equivalents — the rigor that lets a tapeout review actually gate on the number instead of arguing with it.
Your RTL never leaves your network.
RTL is your crown jewel. VoidSense runs where your regressions run — on your hardware, behind your firewall — and starts on open tools, so a team can pilot today without a new EDA license.
Local by default. License-light to start. Enterprise-ready to scale.
A distilled, local-deployable engine runs inside your CI or regression farm; your design never leaves the site. Pilot on a license-free footprint with no new EDA seat, then point the same auditor at your commercial simulator and formal signoff flow behind your firewall when you scale.
Rare founders for a rare problem.
Two founders at the exact intersection this category needs — agentic AI systems and silicon/processor verification — with 30+ combined years and the scar tissue to build an auditor DV managers will actually trust.
Former Systems Lead at a frontier Reality Labs group, driving agentic self-improving systems, and previously inside a major chipmaker's AI division. Was CTO of a CG deep-tech startup acquired by a leading social-media company. A veteran of high-stakes computer vision at a Hollywood-scale visual-effects studio. 3 patents filed in distributed architecture and real-time computer vision.
Former Team Lead at an applied-AI firm shipping ML on real physical systems. Technion-trained Electrical Engineer with 15 years shipping high-performance hardware at a flagship consumer-electronics company and multithreaded processor validation at a blue-chip semiconductor research lab — the silicon-verification half of the pair.